The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing the generation of a bridge between a recess gate and a LPC plug in a part of an isolation layer.
As a design role of a semiconductor device has been reduced, there has been a limit to implementing a required threshold voltage (Vt) target with an existing planar-type channel structure. Therefore, a study on a semiconductor device having a three-dimensional structure of channel has been actively developed, and a semiconductor device having a recess channel and a semiconductor device having a protrusion channel have been proposed as a result of such a study. Furthermore, a semiconductor device having a saddle fin shaped channel, where the recess channel and the protrusion channel are combined, has been proposed.
Compared with the existing semiconductor device having the planar type channel, the semiconductor device having the saddle fin shaped channel increases an effective channel length so that it can secure desired threshold voltage, and the effective channel length is increased so that it has improved current driving characteristics.
Although not shown, in the semiconductor devices having such recess channel and saddle fin shaped channel, not only a gate forming region in an active region is recessed but also an isolation layer part extended to the gate forming area is recessed together. In particular, in the semiconductor device having the saddle fin shaped channel, the isolation structure part extended to the gate forming area is recessed to be deeper than the gate forming area recessed in the active region so that the side surface of the gate forming area recessed in the active region is exposed.
Meanwhile, as the design role of the semiconductor device is reduced, flowable dielectric material such as a spin on dielectric (SOD) layer has been used as trench filling material. However, the SOD layer has a higher wet etching speed to cause an etching loss during a pre cleaning step prior to forming a gate dielectric film.
Therefore, when manufacturing the semiconductor device having the recess channel or the saddle fin shaped channel by applying the SOD layer as the trench filling material according to the prior art, a CD of recess patterns formed on the isolation layer is expanded and thus, a shortage of margins overlapping the gate occurs. As a result, a self align contact fail such as a generation of a bridge between the gate and a LPC plug occurs during a subsequent land plug contact (LPC) process.